■ Cypress Capacitive Sigma-Delta (CSD) provides best-in-class PSoC Creator Design Environment Power trade-offs ■ S Grade: –40 ☌ to +105 ☌ ■ Hibernate and Deep Sleep modes allow wakeup-time versus ■ A Grade: –40 ☌ to +85 ☌ ■ 20 nA Stop Mode with GPIO pin wakeup Temperature Ranges: Low Power 1.71 V to 5.5 V operation ■ Drive modes, strengths, and slew rates are programmable ■ Two low-power comparators that operate in Deep Sleep ■ Any GPIO pin can be CapSense, LCD, analog, or digital Sensing applications on any pin ■ 28-pin SSOP package ■ Two current DACs (IDACs) for general-purpose or capacitive Up to 24 Programmable GPIOs Modes and Channel Sequencer with signal averaging ■ 12-bit, 806 Ksps SAR ADC with differential and single-ended other high reliability digital logic applications Input buffering capability ■ Comparator-based triggering of Kill signals for motor drive and High-bandwidth internal drive, Comparator mode, and ADC ■ Center-aligned, Edge, and Pseudo-random modes ■ One opamp with reconfigurable high-drive external and blocks Programmable Analog ■ Four 16-bit Timer/Counter Pulse-Width Modulator (TCPWM) ■ Up to 4 kB of SRAM Timing and Pulse-Width Modulation ■ Up to 32 kB of flash with Read Accelerator UART, or LIN Slave 1.3, 2.1/2.2 functionality ■ 24 MHz ARM Cortex-M0 CPU with single-cycle multiply communication blocks (SCBs) with reconfigurable I2C, SPI,
■ Automotive Electronics Council (AEC) AEC-Q100 qualified ■ Two independent run-time reconfigurable serial The programmable analog and digital subsystems allow flexibility and in-field tuningģ2-bit MCU Sub-system Serial Communication Platform for new applications and design needs. The PSoC 4100 products will be fully upward compatible with members of the PSoC 4 Standard communication and timing peripherals. Microcontroller with digital programmable logic, high-performance analog-to-digital conversion, opamp with Comparator mode, and The PSoC 4100 product family, based on this platform, is a combination of a It combines programmable and re-configurable analogĪnd digital blocks with flexible automatic routing.
The complete schematics and project files are available to download at google drive.PSoC® 4 is a scalable and reconfigurable platform architecture for a family of mixed-signal programmable embedded systemĬontrollers with an ARM® Cortex™-M0 CPU, while being AEC-Q100 compliant. This is an open hardware Project and this work is licensed under the Creative Commons Attribution 3.0 Unported License. Recommended supply voltage for this system is 5V DC.
If someone interested about real implementation make sure to change RN1 and RN2 to 22K and diode array with 16 - 1N4148 diodes. I never test this system with real parts. The ATmega32 firmware is developed using WinAVR toolset and it design to work with both simulation and real modes. This is customizable system and user can configure number of test lines through single push button (SW1).
This system can test maximum of 16 lines in each test cycle and it indicate the defective line(s) through LCD. The main functionality of this system is to detect open and short circuits in cables and connectors.
I mainly did this project to get familiar with the new Proteus 8 simulator (mainly the new Proteus - ISIS module). This is an ATmega32 based Proteus simulation of 16 line connectivity tester.